1. Technical Field
This disclosure relates to a method of fabricating a semiconductor device and a semiconductor device fabricated thereby, and more particularly, to a method of fabricating a semiconductor device capable of simplifying a direct contact process and a semiconductor device fabricated thereby.
2. Description of the Related Art
As electronic products become thinner and smaller, research is actively conducted on the high integration technology of semiconductor devices used in the electronic products. The high integration technology includes technology for reducing the physical size of components for semiconductor devices and technology for effectively arranging the components in the semiconductor devices. For example, a semiconductor memory device such as a dynamic random access memory (DRAM) includes a plurality of memory cells. The memory cell has a cell transistor, a cell capacitor, and an interconnection. A structure having an area of 8F2 is widely employed for the memory cell. In addition, technologies for reducing the area of the memory cell to 6F2 or 4F2 are widely researched. In this case, F denotes the minimum feature size.
A description can be made for the memory device divided to a memory cell region and a core and peripheral region. Transistors are formed in each region, and the isolated predetermined regions must be electrically connected to each other using a metal interconnection to operate the transistors.
FIGS. 1A to 1E are cross-sectional diagrams illustrating a conventional method of fabricating a semiconductor device. In FIGS. 1A to 1E, the letters “CA” denote a cell region, and the letters “CP” denote a core region.
Referring to FIG. 1A, a semiconductor substrate 1 having a cell region CA and a core region CP is prepared. A trench isolation layer 5 is formed in the semiconductor substrate 1 to define a cell active region 5c and a core active region 5p. A cell gate pattern 9c and a core gate pattern 9p are formed across the cell active region 5c and the core active region 5p, respectively. The cell gate pattern 9c and the core gate pattern 9p may be composed of gate dielectric layers (not shown), gate electrodes 10c and 10p, and capping layer patterns 20c and 20p, respectively, which are sequentially stacked. Subsequently, gate spacers 25 are formed to cover sidewalls of the gate patterns 9c and 9p. Impurity ions may be selectively implanted into the semiconductor substrate of the cell active region 5c using the cell gate pattern 9c and the trench isolation layer 5 as ion implantation masks to form a cell source region 30s and a cell drain region 30d. Similarly, impurity ions may be selectively implanted into the semiconductor substrate of the core active region 5p to form core source and drain regions 30p. Consequently, a cell transistor is formed in the cell region CA of the semiconductor substrate, and a core transistor is formed in the core region CP of the semiconductor substrate. In this case, the core transistor may be an N-channel metal oxide semiconductor (NMOS) transistor or a p-channel MOS (PMOS) transistor. A lower interlayer-insulating layer 35 having a flat top surface is formed on the semiconductor substrate having the gate patterns 9c and 9p. 
Referring to FIG. 1B, a storage node landing pad 45s and a bit line landing pad 45b are formed in the lower interlayer-insulating layer 35 of the cell region CA by a typical self-alignment method. Specifically, the lower interlayer-insulating layer 35 of the cell region CA is patterned to form contact holes for exposing the cell source region 30s and the cell drain region 30d, respectively. Subsequently, a pad conductive layer is formed on the lower interlayer-insulating layer 35 to fill the contact holes. The pad conductive layer is planarized until a top surface of the lower interlayer-insulating layer 35 is exposed, so that the pad conductive layer remains in the contact holes. As a result, a storage node landing pad 45s contacting the cell source region 30s and a bit line landing pad 45b contacting the cell drain region 30d are formed in the lower interlayer-insulating layer 35 of the cell region CA.
Referring to FIG. 1C, an upper interlayer-insulating layer 50 is formed on the entire surface of the semiconductor substrate having the landing pads 45s and 45b. A first photoresist layer pattern 55 is formed on the upper interlayer-insulating layer 50 to expose a top surface of the bit line landing pad 45b. The upper interlayer-insulating layer 50 is etched using the first photoresist layer pattern 55 as an etch mask to form a direct contact hole for bit line 60 which exposes a predetermined region of the bit line landing pad 45b. 
Referring to FIG. 1D, the first photoresist layer pattern (55 in FIG. 1C) is removed. Subsequently, a second photoresist layer pattern 65 is formed on the upper interlayer-insulating layer 50 to expose top surfaces of the core source and drain regions 30p of the core region CP. The upper interlayer-insulating layer 50 is etched using the second photoresist layer pattern 65 as an etch mask to form a direct contact hole for core metal interconnection 70 which exposes the core source and drain regions 30p. 
Referring to FIG. 1E, the second photoresist layer pattern (65 in FIG. 1) is removed. An interconnection conductive layer is formed on the upper interlayer-insulating layer 50 to fill the bit line direct contact hole 60 and the core metal interconnection direct contact hole 70. Subsequently, the interconnection conductive layer is patterned to form a bit line 75b electrically connected to the bit line landing pad 45 and to concurrently form core metal interconnections 75p electrically connected to the core source and drain regions 30p. 
As described above, according to the conventional method of fabricating the semiconductor device using the self alignment method, the processes of forming the bit line direct contact hole 60 and the core metal interconnection direct contact hole 70 in the interlayer-insulating layer must be separately carried out. In highly integrated semiconductor devices, this increases the time and cost associated with fabricating the semiconductor device.
Embodiments of in the invention address these and other disadvantages of the conventional art.